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Reduced interfacial fluctuation leading enhanced mobility in a monolayer MoS2 DG FET under low vertical electric field

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Title
Reduced interfacial fluctuation leading enhanced mobility in a monolayer MoS2 DG FET under low vertical electric field
Author(s)
Hyunjin Ji; Hojoon Yi; Sakong Wonkil; Hyun Kim; Seong Chu Lim
Publication Date
2019-08
Journal
NANOTECHNOLOGY, v.30, no.34, pp.345206 -
Publisher
IOP PUBLISHING LTD
Abstract
Compared to the silicon device whose performance is severely degraded due to the pin-holes and channel inactive space when the channel thickness is less than 1 nm, despite monolayer transition-metal dichalcogenides being the most stable structure to be used as a two-dimensional semiconductor material, precise analysis of the double-gate (DG) field-effect transistor (FET) device structure has hardly been performed thus far. Hence, we analyzed the device operation characteristics of single-gate and DG sweeps in a monolayer MoS2 DG FET structure, where the interfacial carrier behavior is distinguished from both gates by the different gate dielectric materials at the top and bottom. The synchronized DG sweep operation with biasing of V-TG and V-BG (=10 V-TG) increased the carrier mobility by a factor of 4.85 compared with the independent DG sweep. Direct-current analysis and low-frequency noise modeling indicate that the device performance improves under equivalent gate voltages from both sides, because the device operates in a low vertical electric field and the interfacial carrier fluctuation effect is significantly reduced. © 2019 IOP Publishing Ltd Printed in the UK
URI
https://pr.ibs.re.kr/handle/8788114/6125
ISSN
0957-4484
Appears in Collections:
Center for Integrated Nanostructure Physics(나노구조물리 연구단) > Journal Papers (저널논문)
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