Effect of Dislocation Arrays at Grain Boundaries on Electronic Transport Properties of Bismuth Antimony Telluride: Unified Strategy for High Thermoelectric Performance

Abstract

Taming electronic and thermal transport properties is the ultimate goal in the quest to achieve unprecedentedly high performance in thermoelectric (TE) materials. Most state-of-the-art TE materials are inherently narrow bandgap semiconductors, which have an inevitable contribution from minority carriers, concurrently decreasing Seebeck coefficient and increasing thermal conductivity. Nevertheless, the restraint control of minority carrier transport is seldom considered as a key element to enhance the TE figure of merit (zT). Herein, it is verified that the localized dislocation arrays at grain boundaries enable the suppression of minority carrier contribution to electronic transport properties, resulting in an increase of the Seebeck coefficient and the carrier mobility in bismuth antimony tellurides. It is also suggested that the suppression of minority carriers via the generation of dislocation arrays at grain boundaries is an effective and noninvasive strategy to optimize overall electronic transport properties without sacrificing predominant characteristics of majority carriers in TE materials