2D TMD Channel Transistors with ZnO Nanowire Gate for Extended Nonvolatile Memory Applications

Abstract

© 2020 Wiley-VCH GmbH 2D transition metal dichalcogenides (TMDs) have been extensively studied due to their excellent physical properties. Mixed dimensional devices including 2D materials have also been studied, motivated by the possibility of any synergy effect from unique structures. However, only few such studies have been conducted. Here, semiconducting 1D ZnO nanowires are used as thin gate material to support 2D TMD field effect transistors (FETs) and 2D stack-based interface trap nonvolatile memory. For the trap memory, deep level electron traps formed at the first MoS2/second MoS(2)stack interface are exploited, since the first MoS(2)is treated in an atomic layer deposition chamber for a short while. On the one hand, a complementary inverter type memory device can also be achieved using a long single ZnO wire as a common gate to simultaneously support both n- and p-channel TMD FETs. In addition, it is found that the semiconducting ZnO nanowire itself operates as an n-type channel when the TMD materials can become a top-gate to charge the ZnO channel. It means that 2D (bottom gated) and 1D channel (top gated) FETs are respectively operational in a single device structure. The 1D-2D mixed devices seem deserving broad attention in both aspects of novelty and functionality