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Synthesis of wafer-scale uniform molybdenum disulfide films with control over the layer number using a gas phse sulfur precursor

DC Field Value Language
dc.contributor.authorLee.Y-
dc.contributor.authorLee.J-
dc.contributor.authorBark.H-
dc.contributor.authorOh.IK-
dc.contributor.authorRyu.GH-
dc.contributor.authorZonghoon Lee-
dc.contributor.authorKim.H-
dc.contributor.authorCho.JH-
dc.contributor.authorAhn.JH-
dc.contributor.authorChanggu Lee-
dc.date.available2015-04-20T06:06:34Z-
dc.date.created2014-08-11-
dc.date.issued2014-03-
dc.identifier.issn2040-3364-
dc.identifier.urihttps://pr.ibs.re.kr/handle/8788114/1085-
dc.description.abstractWe describe a method for synthesizing large-area and uniform molybdenum disulfide films, with control over the layer number, on insulating substrates using a gas phase sulfuric precursor (H2S) and a molybdenum metal source. The metal layer thickness was varied to effectively control the number of layers (2 to 12) present in the synthesized film. The films were grown on wafer-scale Si/SiO2 or quartz substrates and displayed excellent uniformity and a high crystallinity over the entire area. Thin film transistors were prepared using these materials, and the performances of the devices were tested. The devices displayed an on/off current ratio of 10(5), a mobility of 0.12 cm(2) V (1) s (1) (mean mobility value of 0.07 cm(2) V-1 s(-1)), and reliable operation.-
dc.description.uri1-
dc.language영어-
dc.publisherROYAL SOC CHEMISTRY-
dc.subjectMOS2 ATOMIC LAYERS-
dc.subjectLARGE-AREA-
dc.subjectTHIN-LAYERS-
dc.subjectGRAPHENE-
dc.subjectMONOLAYER-
dc.subjectOPTOELECTRONICS-
dc.subjectSULFURIZATION-
dc.subjectELECTRONICS-
dc.subjectTRANSISTORS-
dc.subjectGROWTH-
dc.titleSynthesis of wafer-scale uniform molybdenum disulfide films with control over the layer number using a gas phse sulfur precursor-
dc.typeArticle-
dc.type.rimsART-
dc.identifier.wosid000332127200041-
dc.identifier.scopusid2-s2.0-84894641277-
dc.identifier.rimsid431ko
dc.date.tcdate2018-10-01-
dc.contributor.affiliatedAuthorChanggu Lee-
dc.identifier.doi10.1039/c3nr05993f-
dc.identifier.bibliographicCitationNANOSCALE, v.6, no.5, pp.2821 - 2826-
dc.citation.titleNANOSCALE-
dc.citation.volume6-
dc.citation.number5-
dc.citation.startPage2821-
dc.citation.endPage2826-
dc.date.scptcdate2018-10-01-
dc.description.wostc98-
dc.description.scptc100-
dc.description.journalClass1-
dc.description.journalRegisteredClassscie-
dc.description.journalRegisteredClassscopus-
dc.subject.keywordPlusMOS2 ATOMIC LAYERS-
dc.subject.keywordPlusLARGE-AREA-
dc.subject.keywordPlusTHIN-LAYERS-
dc.subject.keywordPlusGRAPHENE-
dc.subject.keywordPlusMONOLAYER-
dc.subject.keywordPlusOPTOELECTRONICS-
dc.subject.keywordPlusSULFURIZATION-
dc.subject.keywordPlusELECTRONICS-
dc.subject.keywordPlusTRANSISTORS-
dc.subject.keywordPlusGROWTH-
Appears in Collections:
Center for Integrated Nanostructure Physics(나노구조물리 연구단) > 1. Journal Papers (저널논문)
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