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Gate-tunable graphene-organic interface barrier for vertical transistor and logic inverter

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Title
Gate-tunable graphene-organic interface barrier for vertical transistor and logic inverter
Author(s)
Subir Parui; Mario Ribeiro; Ainhoa Atxabal; Kaushik Bairagi; Elisabetta Zuccatti; C. K. Safeer; Roger Llopis; Felix Casanova; Luis E. Hueso
Publication Date
2018-10
Journal
APPLIED PHYSICS LETTERS, v.113, no.15, pp.153301
Publisher
AMER INST PHYSICS
Abstract
One of the key requirements for efficient organic-electronic devices is the creation of a negligible energy barrier for carrier injection at the metal-organic interface. Here, a graphene-organic interface with an almost negligible energy barrier is demonstrated in a high-performance hybrid heterojunction device. The gate-tunable current-voltage characteristics show that the electronic transport can be tuned from an interface-limited to a bulk-dominated regime by lowering the graphene-organic interface energy barrier. N-type transistors with a PTCDI-C8 organic thin film as an active layer provide an ON-OFF current ratio of similar to 10(7), while similar p-type transistors with a CuPc molecular layer reach an ON-OFF current ratio of similar to 10(5). Furthermore, logic inverters with standby current as low as similar to 1 pA are demonstrated using a combination of both n- and p-type transistors. Published by AIP Publishing. (c) 2018 Aauthor(s)
URI
https://pr.ibs.re.kr/handle/8788114/5102
DOI
10.1063/1.5045497
ISSN
0003-6951
Appears in Collections:
Center for Quantum Nanoscience(양자나노과학 연구단) > 1. Journal Papers (저널논문)
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